With the continuous development of semiconductor technologies, the trend for the technical node of the semiconductor technologies to follow the Moore's law has become smaller and smaller. To adapt the decrease of the technical node, the channel length of the MOSFET has to be continuously decreased. Decreasing the channel length has the benefits such as increasing the integration level of the chip, and increasing the switch speed of the MOSFET, etc.
However, with the continuous shrinking of the channel length, the distance between the source region and the drain region of the semiconductor device has been reduced correspondingly. Thus, the control ability of the gate of the semiconductor device on the channel region is also reduced; and the difficulty for the gate to pinch off the channel is increased. Therefore, it is easier to have the subthreshold leakage phenomenon, i.e., short-channel effects (SCEs), etc.
Thus, to better meet the scaling down requirements of the semiconductor devices, the semiconductor technology has gradually transformed from the conventional planar devices to three-dimensional transistors, for example, fin field effect transistors (FinFETs), etc. In a FinFET, the gate may be able to control the ultra-thin component (fin) from two sides. Thus, comparing with the conventional planar MOSFET, the control ability of the gate to the channel region is significantly enhanced; and it may be able to effectively inhibit the short channel effects. Further, comparing with other types of devices, FinFETs have a better compatibility with the existing integrated circuit manufacturing technology.
However, the performance of the FinFETs formed by the existing fabrication methods may need further improvements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.